Design Review
Grounding Strategy:
Implement a multipoint-grounding scheme for the design. Chassis ground and the PCB signal ground should be at the same potential. Create a multi-point ground structure to form a very low impedance ground path between all boards, including the backplane, and the enclosure. Multi-point grounding will create a low impedance ground structure that will shunt high frequency noise from the PCBs to the chassis. This grounding scheme should be implemented at both the PCB level and with the chassis. The intent of some of these recommendations would maximize flux cancellation between high-speed signals and their corresponding return paths.

Oscillators:
  • Locate components to minimize the trace length of high-speed clock signals. Route high-speed clock signals so that via use is minimized.
  • Add a localized ground fill directly underneath all oscillators. This fill should be connected to the oscillatorís ground pin and to the ground plane through at least two vias.
  • Do not run clock signals close to the edge of the board.

Vias:
  • Vias should be kept as small as possible to minimize discontinuities ("slotting") in the ground and power planes.
  • Use the smallest via possible as manufacturing and other constraints permit. Minimize the use of vias, especially on high-speed clock traces.
  • Monitor the effect adjacent vias have on the power and ground planes. All adjacent vias should have some amount of copper between them on the power and ground planes.

Series Damping Resistors and Filter Capacitors:
  • A coherent signal sources i.e. clock output or semi in-coherent sources i.e. control output signals e.g. CAS, RAS lines in microprocessor applications must contain series damping resistors unless functionality or design notes specify otherwise.
  • It may be necessary to use small capacitors to filter some data, address, and control lines with 10pF capacitors as an example. Note that these values can be optimized during EMI testing.

Bulk Capacitors:
  • Bulk capacitors should be added to strategic locations around the PCB (evenly distributed between the respective voltages of the power distribution circuit)
  • Ensure that at least one bulk capacitor is placed near or around high frequency circuits. The bulk capacitor should be located near the Power-supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.

General Suggestions Regarding Decoupling Capacitors:
  • There should be a minimum of one decoupling capacitor for every power pin on all components in a design. Use 0.01uF decoupling capacitors instead of 0.1uF, clock speeds of most digital designs have increased significantly over the last few years. In general, the 0.01uF capacitors tend to be better for higher frequency designs.
  • Where space permits, add a second decoupling capacitor with a value of 100pF especially around areas on the PCB that contains high frequency circuits. Ideally, every power pin on these high frequency circuits should have 2 decoupling capacitors; in reality, this may prove difficult because of space constraints. Many should be add as is feasible. Capacitors package 0603 can be used to increase density.
  • The second capacitor would add a second resonant point, thereby increasing the attenuation of noise at higher frequencies and giving the ability to "tune" the filtering if needed.
  • All decoupling capacitors should be placed as close as possible to power and ground pins. Make the ground and power connections from the capacitor as short as possible to reduce inductive effects. In addition, make the ground and power connections from the IC as short as possible. Where distance between the IC power or (ground) pin and the capacitor power (or ground) pin is very short, it is acceptable to connect the IC power (or ground) pin to the capacitor power (or ground) pin, and make the connection to the plane through a single via.

PCB Stack-up and Routing:
  • Due to the large number of high-speed buses and clock signals in current digital designs, it is essential that all routing layers have adjacent image planes to provide a low impedance return path for high frequency signals. The table below describes a stack-up example and intended use for each layer.
  • PCB stack-ups should place image planes adjacent to every signal layer. Power planes adjacent to each other would not benefit from the capacitive decoupling effect gained by a dedicated adjacent ground plane. By adding ground planes next to the power planes with an approximate 3-4 mil separation and maintaining separated power-ground planes, additional distributed capacitance would be created which would ultimately lower the characteristic impedance of the power distribution circuits.

The following stack-up is an example of typical stack-up recommendation. Proper Stack-up designs and changes have the greatest effect on reducing EMI in PCB designs and are highly recommended. This stack-up places image planes adjacent to all signal layers. The stack-up also provides excellent flux cancellation between power and ground planes, where the power and ground pairs simulate a large decoupling capacitor and help to control common-mode EMI.

 

1

TOP

Good routing layer

2

GROUND

 

3

SIGNAL

Good routing layer

4

SIGNAL

Best routing layer - use for high speed and critical signals

5

GROUND

 

6

POWER (+5V)

 

7

POWER (+3.3V)

 

8

GROUND

 

9

SIGNAL

Best routing layer - use for high speed and critical signals

10

SIGNAL

Good routing layer

11

GROUND

 

12

BOTTOM

Good routing layer

 

This stack-up should also incorporate the "20-H" rule, which states that the power planes should be 20 times smaller than the distance between the power and ground planes. This action would minimize the fringing effects of RF currents that can lead to higher RF emissions. For example, if the power and ground planes are 4 mils apart, the power plane should be 80 mils smaller than the ground plane on all sides.

  • No routing should be done on any of the ground planes or power planes.
  • Avoid forming gaps in the power and ground planes with vias spaced too closely together (see "Vias" section).
  • Avoid using traces that are crossing gaps on adjacent planes, these gaps are formed by adjacent vias and voids. Any time a trace crosses a gap in an adjacent plane, the impedance of the trace is changed and leads to impedance mis-matches and reflections.
  • No traces should cross over gaps in adjacent planes on the new PCB. If a trace absolutely has to cross a gap in an adjacent power or ground plane, place a capacitor next to the trace where it crosses the gap. The pins of the capacitor should be tied to the nets of the planes on each side of the gap. This capacitor acts as a return path for the high frequency return currents of the trace that crosses the gap.
  • High-speed clock signals should be routed first to minimize trace length, layer jumping, and the use of vias. Next, the highest speed data and address buses should be routed with the same goals in mind. Finally, control signals and less critical signals can be routed.

Oscillator Circuit Power Filtering
The power supply to every clock oscillator and clock generator IC should be individually filter as recommended in the following schematic below. This filter prevents high-speed clock frequencies from corrupting the voltage planes. Multiple capacitors on each side of the ferrite bead allow multiple frequency ranges to be targeted and attenuated by the filter. This technique should be implemented on the power supplies supplying power to critical circuits such as clock oscillators, clock synthesizers, and other high-speed circuits.

The ferrite bead shown in the circuit below and elsewhere in this presentation should be a ferrite bead with a very low equivalent series resistance (ESR). The ESR should be less than 0.4 ohm.


Backplane Interconnect
Filter all supply voltages coming from the backplane. Use the following circuit recommended below. Ensure that the ferrite bead can handle the DC current. Use thick traces on both the source side and load side of this circuit. Size the voltage rating of the capacitors as appropriate for the respective voltages.


Shielding Designs
In general, slots in chassis should be avoided to reduce or eliminate emissions. Use of shielded connectors: The shields of connectors should make a solid 360° connection to the panel.

Most openings in chassis that are not used for connectors are generally large; care should be taken not to misuse of chassis openings. When the slot length is equal to or less than half of the highest frequency wavelength, where the highest frequency equals the reciprocal of the fastest rise time X λ, there is 0dB shielding effectiveness. That is, the shield is not effective. Therefore, the slot length on the rear, front, and the sides of most typical chassis needs to be reduced in order to minimize the effects of EMI.

The following equation determines the shielding effectiveness when slots are introduced into an enclosure, and can be used as a guide to determine slot lengths:

S = 20log [λ/(2 * L)]

where
S = shielding effectiveness
λ(m) = wavelength = 300/f(MHz)
L = length of slot
f = 1/(λ * tr)
tr = fastest rise time

Grounding Designs
Typically Rhein Tech recommends implementing a multipoint grounding scheme for most PCB designs, unless critical circuits that require isolation such as audio/video circuits, isolation of output transformer side in telecommunication products are involved. Each design requires a thorough review in order to determine the proper grounding strategy. The grounding strategy for a product derives from design conferences between Rhein Tech Engineers and our clients.

Multipoint grounding
Implement a multipoint-grounding scheme for most designs. Chassis ground and PCB signal ground should be at the same potential. Create a multi-point ground structure to form a very low impedance ground path between all boards, including the backplane, and the enclosure. Multi-point grounding will create a low impedance ground structure that will shunt high frequency noise from PCBs to chassis. This grounding scheme should be implemented at both the PCB level and with the chassis.

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